AdressWe are looking for a skilled ASIC/FPGA Verification Engineer to work on the next generation communication product design that involves high level design complexity.
Must to have key skills:
. Good command on UVM verification and System Verilog.
. Atleast 3+ years of experience within in ASIC/FPGA verification
. Experience from IP block verification, Multi clock domains, RTL within Verilog, VHDL and/or System Verilog.
. Meritorious in Test bench structuring and design, RTL design.
. Knowledge of test automation with scripting language, such as Python, TCL etc.
Key responsibilities:
. Perform IP block Verification
. Test bench development and test
. Used to work in Scrum teams.
. Good communication skills and a personal drive
. Understanding of Business Requirements and impact analysis
If you think you have the right skills and experience, send your updated profile stating the reference number via e-mail.
Epost: [email protected]
Job Location: Skåne/Göteborg/Stockholm
Note: Application only via e-mail!
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